View ACPL-074L-060E_410355.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

ACPL-071L and ACPL-074L
Single-channel and Dual-channel High Speed 15 MBd CMOS optocoupler with Glitch-Free Power-Up Feature
Data Sheet
Lead (Pb) Free RoHS 6 fully compliant
RoHS 6 fully compliant options available; -xxxE denotes a lead-free product
Description
The ACPL-071L (single-channel) and ACPL-074L (dualchannel) are 15 MBd CMOS optocouplers in SOIC-8 package. The optocouplers utilize the latest CMOS IC technology to achieve outstanding performance with very low power consumption. Basic building blocks of ACPL-071L and ACPL-074L are high speed LEDs and CMOS detector ICs. Each detector incorporates an integrated photodiode, a high speed transimpedance amplifier, and a voltage comparator with an output driver.
Features
* +3.3V and +5 V CMOS compatibility * 30 ns max. pulse width distortion * 40ns max. propagation delay (for 3.3V supply voltage) * 30 ns max. propagation delay skew * High speed: 15 MBd min * 10 kV/s minimum common mode rejection * -40 to 105C temperature range * Glitch-Free Power-Up Feature
ACPL-071L
Component Image
NC ANODE CATHODE NC
1 2 8 7 6
* Safety and regulatory approvals pending:
VDD NC VO
* UL recognized * 3750 V rms for 1 min. per UL 1577 * CSA component acceptance Notice #5 * IEC/EN/DIN EN 60747-5-2 approved Option 060
3 4 SHIELD
Applications
* Digital field bus isolation: * CANBus, RS485, USB * Multiplexed data transmission * Computer peripheral interface * Microprocessor system interface * DC/DC converter
5
GND
ACPL-074L ANODE1 1 8 VDD 7 CATHODE1 CATHODE2 2 3 6 ANODE2 4 SHIELD 5 Vo2 GND Vo1
TRUTH TABLE LED OFF ON VO, OUTPUT
H L
A 0.1uF bypass capacitor must be connected between pins 5 and 8.
CAUTION: It is advised that normal static precautions be taken in handling and assembly of this component to prevent damage and/or degradation which may be induced by ESD.
Ordering Information
ACPL-071L/074L are UL Recognized with 3750 Vrms for 1 minute per UL1577. Option Part number
ACPL-071L
RoHS Compliant
-000E -500E -060E -560E -000E -500E -060E -560E
Package
Surface Mount
X X X X X X X X
Gull Wing
Tape& Reel
X
UL 5000 Vrms/ 1 Minute rating
IEC/EN/DIN EN 60747-5-2
Quantity
100 per tube 1500 per reel
SO-8
X X X X X X X
100 per tube 1500 per reel 100 per tube 1500 per reel 100 per tube 1500 per reel
ACPL-074L
SO-8
To order, choose a part number from the part number column and combine with the desired option from the option column to form an order entry. Example 1: ACPL-071L-500E to order product of Small Outline SO-8 package in Tape and Reel packaging in RoHS compliant. Example 2: ACPL-074L-000E to order product of Small Outline SO-8 package in tube packaging and RoHS compliant. Option datasheets are available. Contact your Avago sales representative or authorized distributor for information.
2
Package Dimensions
ACPL-071L and ACPL-074L (Small Outline S0-8 Package)
LAND PATTERN RECOMMENDATION
8 3.937 0.127 (0.155 0.005) 1
7
6 XXXV YWW
5
5.994 0.203 (0.236 0.008) TYPE NUMBER (LAST 3 DIGITS) DATE CODE 7.49 (0.295)
PIN ONE 0.406 0.076 (0.016 0.003)
2
3
4 1.270 BSC (0.050)
1.9 (0.075)
0.64 (0.025)
* 5.080 0.127 (0.200 0.005) 3.175 0.127 (0.125 0.005)
7
45 X
0.432 (0.017)
1.524 (0.060)
0~7
0.228 0.025 (0.009 0.001)
0.203 0.102 (0.008 0.004) * TOTAL PACKAGE LENGTH (INCLUSIVE OF MOLD FLASH) 5.207 0.254 (0.205 0.010) DIMENSIONS IN MILLIMETERS (INCHES). LEAD COPLANARITY = 0.10 mm (0.004 INCHES) MAX. OPTION NUMBER 500 NOT MARKED. NOTE: FLOATING LEAD PROTRUSION IS 0.15 mm (6 mils) MAX. 0.305 MIN. (0.012)
3
Solder Reflow Thermal profile
300 PREHEATING RATE 3C + 1C/-0.5C/SEC. REFLOW HEATING RATE 2.5C 0.5C/SEC. PEAK TEMP. 245C PEAK TEMP. 240C
200 TEMPERATURE (C) 160C 150C 140C
2.5 C 0.5 C/SEC. 30 SEC. 3 C + 1C/-0.5C 30 SEC.
PEAK TEMP. 230C
SOLDERING TIME 200C
100
PREHEATING TIME 150C, 90 + 30 SEC. ROOM TEMPERATURE
50 SEC. TIGHT TYPICAL LOOSE
0
0
50
100 TIME (SECONDS)
150
200
250
Note: Non-halide flux should be used.
Recommended Pb-Free IR Flow
TIME WITHIN 5 C of ACTUAL PEAK TEMPERATURE Tp 217 C TL TEMPERATURE Tsmax Tsmin 150 - 200 C 260 +0/-5 C RAMP-UP 3 C/SEC. MAX. tp 20-40 SEC.
Regulatory Information
The ACPL-071L and ACPL-074L have been approved by the following organizations:
UL
Recognized under UL 1577, component recognition program, File E55361.
RAMP-DOWN 6 C/SEC. MAX.
CSA
Approved under CSA Component Acceptance Notice #5, File CA88324.
ts PREHEAT 60 to 180 SEC. 25
tL
60 to 150 SEC.
IEC/EN/DIN EN 60747-5-2
Approved under: IEC 60747-5-2:1997 + A1:2002
t 25 C to PEAK TIME
EN 60747-5-2:2001 + A1:2002 DIN EN 60747-5-2 (VDE 0884Teil 2):2003-01 (Option 060 only)
Notes: The time from 25 C to peak temperature = 8 minutes max. Tsmax = 200 C, Tsmin = 150 C Non-halide ux should be used
4
Insulation and Safety Related Specifications
Parameter
Minimum External Air Gap (Clearance) Minimum External Tracking (Creepage) Minimum Internal Plastic Gap (Internal Clearance) Tracking Resistance CTI (Comparative Tracking Index) Isolation Group
Symbol
L(I01) L(I02)
Value
4.9 4.8 0.08 175 IIIa
Units
mm mm mm Volts
Conditions
Measured from input terminals to output terminals, shortest distance through air. Measured from input terminals to output terminals, shortest distance path along body. Insulation thickness between emitter and detector; also known as distance through insulation. DIN IEC 112/VDE 0303 Part 1 Material Group (DIN VDE 0110, 1/89, Table 1)
All Avago Technologies data sheets report the creepage and clearance inherent to the optocoupler component itself. These dimensions are needed as a starting point for the equipment designer when determining the circuit insulation requirements. However, once mounted on a printed circuit board, minimum creepage and clearance requirements must be met as specified for individual equipment standards. For creepage, the shortest distance
path along the surface of a printed circuit board between the solder fillets of the input and output leads must be considered. There are recommended techniques such as grooves and ribs which may be used on a printed circuit board to achieve desired creepage and clearances. Creepage and clearance distances will also change depending on factors such as pollution degree and insulation level.
5
IEC/EN/DIN EN 60747-5-2 Insulation Related Characteristics (Option 060) Description
Installation classification per DIN VDE 0110/1.89, Table 1 for rated mains voltage 150 V rms for rated mains voltage 300 V rms Climatic Classification Pollution Degree (DIN VDE 0110/1.89) Maximum Working Insulation Voltage Input to Output Test Voltage, Method b VIORM x 1.875 = VPR, 100% Production Test with tm = 1 sec, Partial Discharge < 5 pC Input to Output Test Voltage, Method a VIORM x 1.5 = VPR, Type and Sample Test, tm = 60 sec, Partial Discharge < 5 pC Highest Allowable Overvoltage (Transient Overvoltage, tini = 10 sec) Safety Limiting Values (Maximum values allowed in the event of a failure, also see Thermal Derating curve, Figure 11.) Case Temperature Input Current Output Power Insulation Resistance at TS, V10 = 500 V VIORM VPR
Symbol
Option 060
I-IV I-III 55/105/21 2 560 1050
Units
VPEAK VPEAK
VPR
840
VPEAK
VIOTM
4000
VPEAK
Ts Is, INPUT Ps,OUTPUT RIO
150 150 600 109
C mA mW
Absolute Maximum Ratings
Parameter
Storage Temperature Ambient Operating Temperature Supply Voltages Output Voltage Average Forward Input Current Average Output Current Lead Solder Temperature Solder Reflow Temperature Profile
Symbol
TS TA VDD VO IF Io
Min.
-55 -40 0 -0.5 -
Max.
+125 +105 6.0 VDD +0.5 20.0 10.0
Units
C C Volts Volts mA mA
260C for 10 sec., 1.6 mm below seating plane See Solder Reflow Temperature Profile Section
Recommended Operating Conditions
Parameter
Ambient Operating Temperature Supply Voltages Input Current (ON) Supply Voltage Slew Rate[1]
Symbol
TA VDD IF SR
Min.
-40 4.5 3.0 9 0.5
Max.
+105 5.5 3.6 18 500
Units
C V V mA V/ms
6
Electrical Specifications
Over recommended temperature (TA = -40C to +105C), 3.0V VDD 3.6V and 4.5 V VDD 5.5 V. All typical specifications are at TA=+25C, VDD= +3.3V. Parameter
Input Forward Voltage Input Reverse Breakdown Voltage
Symbol
VF BVR
Part Number
Min.
1.3 5.0 VDD-1 VDD-1
Typ.
1.5
Max.
1.8
Units
V V
Test Conditions
IF = 14mA IR = 10 A IF = 0, IO = -4 mA, VDD=3.3V IF = 0, IO = -4 mA, VDD=5V IF = 14mA, IO =4mA, VDD=3.3V IF = 14mA, IO = 4mA, VDD=5V IOL = 20 A IF = 14 mA IF = 14 mA IF = 0 IF = 0
Logic High Output Voltage VOH Logic Low Output Voltage VOL Input Threshold Current Logic Low Output Supply Current Logic Low Output Supply Current ITH IDDL IDDH ACPL-071L ACPL-074L ACPL-071L ACPL-074L
VDD-0.3 VDD-0.2 0.35 0.2 4.5 4.1 8.3 3.8 7.6 0.8 0.8 8.8 6.0 12.0 6.0 12.0
V V V V mA mA mA mA mA
Switching Specifications
Over recommended temperature (TA = -40C to +105C), 3.0V VDD 3.6V and 4.5 V VDD 5.5 V. All typical specifications are at TA=+25C, VDD = +3.3V. Parameter
Propagation Delay Time to Logic Low Output[2]
Symbol
tPHL
Min.
Typ.
29
Max.
40 50
Units
ns ns ns ns ns
Test Conditions
IF = 14mA, CL= 15pF, VDD=3.3V CMOS Signal Levels IF = 14mA, CL= 15pF, VDD=5V CMOS Signal Levels IF = 14mA, CL= 15pF, VDD=3.3V, CMOS Signal Levels IF = 14mA, CL= 15pF, VDD=5V, CMOS Signal Levels IF = 14mA, CL= 15pF, VDD=3.3V, CMOS Signal Levels IF = 14mA, CL= 15pF, VDD=5V, CMOS Signal Levels IF = 14mA, CL= 15pF CMOS Signal Levels IF = 14mA, CL= 15pF CMOS Signal Levels IF = 14mA, CL= 15pF CMOS Signal Levels VCM = 1000 V, TA = 25C, IF = 0 mA VCM = 1000 V, TA = 25C, IF = 14 mA
Propagation Delay Time to Logic High Output[2]
tPLH
22
40 50
Pulse Width Pulse Width Distortion[3]
tPW |PWD |
66.7 0 7 25 30
ns ns ns ns ns kV/s kV/s
Propagation Delay Skew[4] Output Rise Time (10% - 90%) Output Fall Time (90% - 10%) Common Mode Transient Immunity at Logic High Output[5] Common Mode Transient Immunity at Logic Low Output[6]
tPSK tR tF | CMH | | CML | 10 10 20 25 15 15
30
7
Package Characteristics
All Typical at TA = 25C. Parameter
Input-Output Insulation
Symbol
II-O
Min.
Typ.
Max.
1.0
Units
A
Test Conditions
45% RH, t = 5 s VI-O = 3 kV DC, TA = 25C RH 50%, t = 1 min., TA = 25C V I-O = 500 V dc f = 1 MHz, TA = 25C
Input-Output Momentary Withstand Voltage Input-Output Resistance Input-Output Capacitance
VISO R I-O C I-O
3750 10 12 0.6
Vrms W pF
Notes: 1. Slew rate of supply voltage ramping is recommended to ensure no glitch more than 1V to appear at the output pin. 2. tPHL propagation delay is measured from the 50% level on the rising edge of the input pulse to the 50% level of the falling edge of the VO signal. tPLH propagation delay is measured from the 50% level on the falling edge of the input pulse to the 50% level of the rising edge of the VO signal. 3. PWD is defined as |tPHL - tPLH|. 4. tPSK is equal to the magnitude of the worst case difference in tPHL and/or tPLH that will be seen between units at any given temperature within the recommended operating conditions. 5. CMH is the maximum tolerable rate of rise of the common mode voltage to assure that the output will remain in a high logic state. 6. CML is the maximum tolerable rate of fall of the common mode voltage to assure that the output will remain in a low logic state.
1000 100 IF -FORWARD CURRENT-mA 10 1 0.1 0.01 0.001 1.1 VF
Ith -INPUT THRESHOLD CURRENT-mA
IF TA=25C
6 5 4 3 2 1 0 -40 -20 0 20 40 60 TA -TEMPERATURE-o C 80 I oL =20uA 5V 3.3V
1.2
1.3 1.4 1.5 V F -FORWARD VOLTAGE-V
1.6
100
120
Figure 1. Typical input diode forward characteristic.
Figure 2. Typical input threshold current vs. temperature.
IDDH-LOGIC HIGH OUTPUT SUPPLY CURRENT -mA
IDDl -LOGIC LOW OUTPUT SUPPLY CURRENT-mA
12 10 8 6 4 2 0 -40 -20 0 20 40 60 T A -TEMPERATURE-o C VDD=5.0V VDD=3.3V 80 100
12 10 8 6 4 2 0 -40 -20 0 VDD=5.0V VDD=3.3V 20 40 60 T A -TEMPERATURE-oC 80 100
Figure 3. Typical logic high O/P supply current vs. temperature for ACPL-074L.
Figure 4. Typical logic low O/P supply current vs. temperature for ACPL-074L.
8
50 45 40 35 TPHL CH2 30 25 20 15 PWD CH1 10 VDD=5V 5 TA=25C 0 6 7 8
tp - PROPAGATION DELAY; PWD-PULSE WIDTH DISTORTION - ns
tp- PROPAGATION DELAY; PWD-PULSE WIDTH DISTORTION - ns
TPHL CH1 TPLH CH2 TPLH CH1 PWD CH2
50 45 40 35 30 25 20 15 10 5 0 TPHL CH2 TPLH CH2
TPHL CH1
TPLH CH1 PWD CH1 VDD=3.3V TA=25C 6 7 8 9 10 11 12 13 14 IF - PULSE INPUT CURRENT - mA 15 16 PWD CH2
9 10 11 12 13 14 IF - PULSE INPUT CURRENT - mA
15
16
Figure 5. Typical switching speed vs. pulse input current at 5V supply voltage.
Figure 6. Typical switching speed vs. pulse input current at 3.3V supply voltage.
1.65 1.6 V F -FORWARD VOLTAGE-V 1.55 1.5 1.45 1.4 1.35 -40 -20 0 20 40 60 TA -TEMPERATURE-oC 80 100
Application Information
Bypassing and PC Board Layout
The ACPL-071L and ACPL-074L optocouplers are extremely easy to use. ACPL-071L and ACPL-074L provide CMOS logic output due to the high-speed CMOS IC technology used. The external components required for proper operation are the input limiting resistor and the output bypass capacitor. Capacitor values should be between 0.01 F and 0.1 F. For each capacitor, the total lead length between both ends of the capacitor and the power-supply pins should not exceed 20 mm.
Figure 7 Typical VF vs. temperature.
1 IF GND1 2 3 4 ACPL-071L C = 0.01mF to 0.1mF
XXX YWW
8 7 NC 6 5 GND2 C
VDD
IF1 GND 1
1 2 3 4 ACPL-074L XXX YWW
8 7 6 5
C
VDD VO1 VO2
VO
GND 1 IF2
GND 2
Figure 8. Recommended printed circuit board layout
9
Propagation Delay, Pulse-Width Distortion and Propagation Delay Skew
Propagation delay is a figure of merit which describes how quickly a logic signal propagates through a system. The propagation delay from low to high (tPLH) is the amount of time required for an input signal to propagate to the output, causing the output to change from low to high. Similarly, the propagation delay from high to low (tPHL) is the amount of time required for the input signal to propagate to the output, causing the output to change from high to low (see Figure 9). Pulse-width distortion (PWD) results when tPLH and tPHL differ in value. PWD is defined as the difference between tPLH and tPHL and often PWD is defined as the difference between tPLH and tPHL and often determines the maximum data rate capability of a transmission system. PWD can be expressed in percent by dividing the PWD (in ns) by the minimum pulse width (in ns) being transmitted. Typically, PWD on the order of 20-30% of the minimum pulse width is tolerable; the exact figure depends on the particular application (RS232, RS422, T-1, etc.). Propagation delay skew, tPSK, is an important parameter to consider in parallel data applications where synchronization of signals on parallel data lines is a concern. If the parallel data is being sent through a group of optocouplers, differences in propagation delays will cause the data to arrive at the outputs of the optocouplers at different times. If this difference in propagation delays is large enough, it will determine the maximum rate at which parallel data can be sent through the optocouplers. Propagation delay skew is defined as the difference between the minimum and maximum propagation delays,
IF 50%
either tPLH or tPHL, for any given group of optocouplers which are operating under the same conditions (i.e., the same supply voltage, output load, and operating temperature). As illustrated in Figure 10, if the inputs of a group of optocouplers are switched either ON or OFF at the same time, tPSK is the difference between the shortest propagation delay, either tPLH or tPHL, and the longest propagation delay, either tPLH or tPHL. As mentioned earlier, tPSK can determine the maximum parallel data transmission rate. Figure 10 is the timing diagram of a typical parallel data application with both the clock and the data lines being sent through optocouplers. The figure shows data and clock signals at the inputs and outputs of the optocouplers. To obtain the maximum data transmission rate, both edges of the clock signal are being used to clock the data; if only one edge were used, the clock signal would need to be twice as fast. Propagation delay skew represents the uncertainty of where an edge might be after being sent through an optocoupler. Figure 10 shows that there will be uncertainty in both the data and the clock lines. It is important that these two areas of uncertainty not overlap, otherwise the clock signal might arrive before all of the data outputs have settled, or some of the data outputs may start to change before the clock signal has arrived. From these considerations, the absolute minimum pulse width that can be sent through optocouplers in a parallel application is twice tPSK. A cautious design should use a slightly longer pulse width to ensure that any additional uncertainty in the rest of the circuit does not cause a problem.
DATA INPUTS
VO
50%, CMOS tPSK
CLOCK
IF
50%
DATA OUTPUTS 50%, CMOS CLOCK tPSK Figure 10. Parallel data transmission example tPSK
VO
Figure 9. Propagation delay and skew waveform
10
The tPSK specified optocouplers offer the advantages of guaranteed specifications for propagation delays, pulsewidth distortion and propagation delay skew over the recommended temperature, and power supply ranges.
Speed Improvement
A peaking capacitor can be placed across the input current limit resistor (Figure 11) to achieve enhanced speed performance. The value of the peaking cap is dependent to the rise and fall time of the input signal and supply voltages and LED input driving current (If ). Figure 12 shows significant improvement of propagation delay and pulse with distortion with added peak capacitor at driving current of 14mA and 3.3V or 5V power supply.
Cpeak R drv =50
+ V in -
Powering Sequence
VDD needs to achieve a minimum level of 3.0V before powering up the output connecting component.
Input Limiting Resistors
ACPL-071L and ACPL-074L are direct current driven (Figure 8), and thus eliminate the need for input power supply. To limit the amount of current flowing through the LED, it is recommended that a 210ohm resistor is connected in series with anode of LED (i.e. Pin 2 for ACPL-071L and Pin 1 and 4 for ACPL-074L) at 5V input signal. At 3.3V input signal, it is recommended to connect 80ohm resistor in series with anode of LED. The recommended limiting resistors are based on the assumption that the driver output impedence is 50 (as shown in Figure 11).
VDD2 R limit 0.1F VO
GND1
SHIELD
GND 2
Figure 11 Connection of peaking capacitor (Cpeak) in parallel of the input limiting resistor (Rllimit) to improve speed performance
t p - PROPAGATION DELAY; PWD-PULSE WIDTH DISTORTION -ns
tPHL With peaking cap Without peaking cap
t p - PROPAGATION DELAY; PWD-PULSE WIDTH DISTORTION -ns
35.00 30.00 25.00 20.00 15.00 10.00 5.00 0.00 -40 |PWD| -20 0 tPHL tPLH
30.00 25.00 20.00 15.00 10.00 5.00 0.00 -40 -20 0 tPHL tPLH
tPHL
tPLH With peaking cap Without peaking cap |PWD|
tPLH
20 40 60 TA - TEMPERATURE - o C
80
100
20 40 60 TA - TEMPERATURE - o C
80
100
(i) VDD=3.3V, Cpeak=100pF, Rlimit=80
(ii) VDD=5V, Cpeak=100pF, Rlimit=210
Figure 12. Improvement of tp and PWD with added 100pF peaking capacitor in parallel of input limiting resistor.
11
VCM A B IF
Rlimit
V DD2 V O monitoring VCM 0.1F note VO VO 0V VDD
VCM (PEAK) SWITCH AT A: I F = 0 mA SWITCH AT B: I F = 14 mA VO (min.) VO (max.) CM L CM H
SHIELD Pulse Gen. Zo=50 + -
GND 2
GND2
Figure 13. Test circuit for common mode transient immunity and typical waveforms. Rtotal is the total resistance of the driver output impedence (which is assumed to be 50 ) and the limiting resistor (Rtotal=Rdrv+Rlimit) .
For product information and a complete list of distributors, please go to our web site:
www.avagotech.com
Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies Limited in the United States and other countries. Data subject to change. Copyright (c) 2005-2008 Avago Technologies Limited. All rights reserved. AV02-0963EN - June 2, 2008

▲Up To Search▲

Price & Availability of ACPL-074L-060E

	To Download ACPL-074L-060E Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .